The present invention relates generally to dynamic read-write randomly accessible memory devices (DRAMs), more particularly to dynamic RAMs which use a grooved-surface structure to achieve a very high density of capacitive memory elements, and especially to a capacitor-plate bias generator circuit for such memory devices.
Digital information is stored in the form of capacitive charge in a matrix-array of many capacitive elements in the DRAM memory device. Recently, certain advances in the manner of forming the capacitive memory elements have increased the density of memory elements on each silicon wafer or chip.
One such advance has involved the provision of a grooved-surface microstructure on the silicon wafer, such that the surface area available for the formation of capacitive memory elements is increased substantially as compared to the planar structures formerly in use. However, the use of such a groove technology in forming the capactive elements has resulted in changes in the capacitor structure which have set new requirements for the capacitor-plate bias voltage, as will appear from the detailed discussions later in this patent application.
In order that the newer groove technology results in reliable memory devices having the desired characteristics of high density and very low soft error rate, a new capacitor-plate bias generator circuit was needed. For reasons which will be discussed in the later portions of this application, the bias generator must generate a voltage which is higher than the V.sub.CC voltage in use in the device, must be stable over a wide range of operating conditions, and must be insensitive to normal process and temperature variations.